Publications

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Tohidi, M., Madsen, J. K. & Moradi, F. (2018). Low-Power, Low-Noise Epileptic-Seizure Detection System with High Accuracy Using EEG Signals. Poster-session præsenteret på Biomedical Circuits and Systems Conference, Cleveland, USA. https://www.epapers.org/biocas2018/ESR/paper_details.php?PHPSESSID=ok076vdjtkiu7kett65d8hk0g0&paper_id=6066

Bagheriye, L., Toofan, S., Saeidi, R. & Moradi, F. (2018). Offset-Compensated High-Speed Sense Amplifier for STT-MRAMs. I E E E Transactions on Very Large Scale Integration (VLSI) Systems, 26(6), 1051-1058. https://doi.org/10.1109/TVLSI.2018.2808140

Varghani, A., Peiravi, A. & Moradi, F. (2018). Perpendicular STT_RAM Cell in 8nm Technology Node Using Co1/Ni3(111)||Gr2||Co1/Ni3(111) Structure as Magnetic Tunnel Junction. Journal of Magnetism and Magnetic Materials, 452, 10-16. https://doi.org/10.1016/j.jmmm.2017.12.021

Zeinali, B., Karsinos, D. & Moradi, F. (2018). Progressive Scaled STT-RAM for Approximate Computing in Multimedia Applications. IEEE Transactions on Circuits and Systems II: Express Briefs, 65(7), 938-942. https://doi.org/10.1109/TCSII.2017.2738844

Assarzadeh, M., Saberi, M., Tohidi, M. & Moradi, F. (2017). A Low-Power Time-Based Phase-Domain Analog-to-Digital Converter. I 2016 IEEE International Conference on Electronics, Circuits and Systems, ICECS 2016: ICECS 2016 (s. 21-24). Artikel 7841122 IEEE Press. https://doi.org/10.1109/ICECS.2016.7841122

Akbari, M., Hashemipour, O. & Moradi, F. (2017). Design and Analysis of an Ultra-Low-Power Second-Order Asynchronous Delta–Sigma Modulator. Circuits, Systems, and Signal Processing, 36(12), 4919-4936. https://doi.org/10.1007/s00034-017-0658-7

Zeinali, B., Madsen, J. K., Raghavan, P. & Moradi, F. (2017). Low-leakage sub-threshold 9T-SRAM cell in 14-nm FinFET technology. International Journal of Circuit Theory and Applications, 45(11), 1647-1659. https://doi.org/10.1002/cta.2280

Tohidi, M., Madsen, J. K., Heck, M. & Moradi, F. (2017). Low-Power Comparator in 65-nm CMOS with Reduced Delay Time. I 2016 IEEE International Conference on Electronics, Circuits and Systems, ICECS 2016: ICECS 2016 (s. 736-739). Artikel 7841307 IEEE Press. https://doi.org/10.1109/ICECS.2016.7841307

Zeinali, B., Esmaeili, M., Madsen, J. K. & Moradi, F. (2017). Multilevel SOT-MRAM Cell with a Novel Sensing Scheme for High-Density Memory Applications. I 2017 47th European Solid-State Device Research Conference, ESSDERC 2017: ESSDERC 2017 (s. 172-175). Artikel 8066619 IEEE. https://doi.org/10.1109/ESSDERC.2017.8066619

Ghanatian, H., Hosseini, S. E., Zeinali, B. & Moradi, F. (2017). Quasi-Schottky-Barrier UTBB SOI MOSFET for Low-Power Robust SRAMs. IEEE Transactions on Electron Devices, 64(4), 1575-1582. Artikel 7875448. https://doi.org/10.1109/TED.2017.2672968

Farkhani, H., Tohidi, M., Peiravi, A., Madsen, J. K. & Moradi, F. (2017). STT-RAM energy reduction using self-referenced differential write termination technique. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 25(2), 476-487. Artikel 7522092. https://doi.org/10.1109/TVLSI.2016.2588585

Zeinali, B., Madsen, J. K., Raghavan, P. & Moradi, F. (2017). Ultra-Fast SOT-MRAM Cell with STT Current for Deterministic Switching. I Proceedings - 35th IEEE International Conference on Computer Design, ICCD 2017: ICCD 2017 (s. 463-468). Artikel 8119254 IEEE. https://doi.org/10.1109/ICCD.2017.81

Nasserian, M., Peiravi, A. & Moradi, F. (2016). A 1.62 µW 8-Channel Ultra-High Input Impedance EEG Amplifier for Dry and Non-Contact Biopotential Recording Applications. I 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016: VLSI-SoC (Bind 2016). Artikel 7753539 IEEE Press. https://doi.org/10.1109/VLSI-SoC.2016.7753539

Tohidi, M., Madsen, J. K., Heck, M. & Moradi, F. (2016). A Low-Power Analog Front-End Neural Acquisition Design for Seizure Detection. I 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016: VLSI-SoC (Bind 2016). Artikel 7753541 IEEE Press. https://doi.org/10.1109/VLSI-SoC.2016.7753541

Nasserian, M., Kafi-Kangi, M., Maymandi Nejad, M. & Moradi, F. (2016). A Low-Power Fast Tag Comparator by Modifying Charging Scheme of Wide Fan-in Dynamic OR gates. Integration, 52(January), 129-141. https://doi.org/10.1016/j.vlsi.2015.09.004

Zeinali, B., Madsen, J. K., Raghavan, P. & Moradi, F. (2016). A Novel Nondestructive Bit-Line Discharging Scheme for Deep Submicrometer STT-RAM. Afhandling præsenteret på The 34th IEEE International Conference on Computer Design, Phoenix, USA.

Zhou, X., Li, Q., Kilsgaard, S., Moradi, F., Kappel, S. & Kidmose, P. (2016). A Wearable Ear-EEG Recording System Based on Dry-Contact Active Electrodes. I 2016 IEEE Symposium on VLSI Circuits, VLSI Circuits 2016: VLSI Circuits 2016 (Bind 2016). Artikel 7573559 IEEE Press. https://doi.org/10.1109/VLSIC.2016.7573559

Varghani, A., Peiravi, A. & Moradi, F. (2016). Graphene-Based STT-RAM Cell with Improved Switching for Scaled Technology Nodes. I E E E Transactions on Magnetics, 52(1), Artikel 1600108. https://doi.org/10.1109/TMAG.2015.2473135

Farkhani, H., Peiravi, A. & Moradi, F. (2016). Low-Energy Write Operation for 1T-1MTJ STT-RAM Bitcells With Negative Bitline Technique. I E E E Transactions on Very Large Scale Integration (VLSI) Systems, 24(4), 1593-1597. Artikel 7208896. https://doi.org/10.1109/TVLSI.2015.2459726

Lundager, K., Zeinali, B., Tohidi, M., Madsen, J. K. & Moradi, F. (2016). Low Power Design for Future Wearable and Implantable Devices. Journal of Low Power Electronics and Applications, 6(4), Artikel 20. https://doi.org/10.3390/jlpea6040020

Kharghanian, R., Peiravi, A. & Moradi, F. (2016). Pain detection from facial image using unsupervised feature learning approach. Proceedings of the International Conference of the IEEE Engineering in Medicine and Biology Society , 2016, 419-422. https://doi.org/10.1109/EMBC.2016.7590729

Moradi, F., Tohidi, M., Zeinali, B. & Madsen, J. K. (2015). 8T-SRAM Cell with Improved Read and Write Margins in 65 nm CMOS Technology. I L. Claesen, M.-T. Sanz-Pascual, R. Reis & A. Sarmiento-Reyes (red.), VLSI-SoC: Internet of Things Foundations: 22nd IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2014, Playa del Carmen, Mexico, October 6–8, 2014, Revised and Extended Selected Papers (Bind 464, s. 95-109). Springer. https://doi.org/10.1007/978-3-319-25279-7_6

Farkhani, H., Peiravi, A. & Moradi, F. (2015). A New Write Assist Technique for SRAM Design in 65nm CMOS Technology. Integration, 50, 16-27. https://doi.org/10.1016/j.vlsi.2015.01.001

Moradi, F. & Tohidi, M. (2015). Low-Voltage 9T FinFETSRAM Cell for Low-Power Applications. I Proceedings of the 28th IEEE International System on Chip Conference (SOCC) (s. 149-153). IEEE. https://doi.org/10.1109/SOCC.2015.7406929

Farkhani, H., Peiravi, A., Madsen, J. K. & Moradi, F. (2015). STT-RAM Write Energy Consumption Reduction by Differential Write Termination Method. I 2015 IEEE International Symposium on Circuits and Systems (ISCAS) (Bind 2015, s. 2936-2939). IEEE. https://doi.org/10.1109/ISCAS.2015.7169302

Zeinali, B., Madsen, J. K., Raghavan, P. & Moradi, F. (2015). Sub-Threshold SRAM Design in 14Nm FinFET Technology with Improved Access Time and Leakage Power. I Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI) (Bind 2015, s. 74-79). IEEE. https://doi.org/10.1109/ISVLSI.2015.73

Farkhani, H., Peiravi, A., Madsen, J. K. & Moradi, F. (2015). Symmetric Write Operation for 1T-1MTJ STT-RAM Cells Using Negative Bitline Technique. I Proceedings of the 28th IEEE International System on Chip Conference (SOCC) (Bind 2015, s. 215-220). IEEE. http://ieeexplore.ieee.org.ez.statsbiblioteket.dk:2048/xpl/articleDetails.jsp?arnumber=7406948&newsearch=true&queryText=10.1109%2FSOCC.2015.7406948%20

Farkhani, H., Peiravi, A. & Moradi, F. (2014). A new asymmetric 6T SRAM cell with a write assist technique in 65 nm CMOS technology. Microelectronics Journal, 45(11), 1556-1565. https://doi.org/10.1016/j.mejo.2014.09.006

Farkhani, H., Peiravi, A., Madsen, J. K. & Moradi, F. (2014). Comparative study of FinFETs versus 22nm bulk CMOS technologies: SRAM design perspective. I 27th IEEE International System on Chip Conference: SOCC 2014 (s. 449-454). Artikel 6948971 IEEE Computer Society Press. https://doi.org/10.1109/SOCC.2014.6948971

Moradi, F. & Madsen, J. K. (2014). Improved read and write margins using a novel 8T-SRAM cell. I L. Garcia (red.), 2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC): Conference Proceedings (s. 1-5). IEEE. https://doi.org/10.1109/VLSI-SoC.2014.7004186

Moradi, F., Panagopoulos, G., Karakonstantis, G., Farkhani, H., Wisland, D. T., Madsen, J. K., Mahmoodi, H. & Roy, K. (2014). Multi-level wordline driver for robust SRAM design in nano-scale CMOS technology. Microelectronics Journal, 45(1), 23-34. https://doi.org/10.1016/j.mejo.2013.09.009

Moradi, F. & Madsen, J. K. (2014). Robust subthreshold 7T-SRAM cell for low-power applications. Midwest Symposium on Circuits and Systems. Conference Proceedings, 893-896. Artikel 6908559. https://doi.org/10.1109/MWSCAS.2014.6908559

Moradi, F., Vu Cao, T., Vatajelu, E. I., Peiravi, A., Mahmoodi, H. & Wisland, D. (2013). Domino logic designs for high-performance and leakage-tolerant applications. Integration, 46(3), 247–254. https://doi.org/10.1016/j.vlsi.2012.04.005

Moradi, F. (2012). Datapath design using asymmetrically-doped FinFET. Midwest Symposium on Circuits and Systems. Conference Proceedings, 21-24. https://doi.org/10.1109/MWSCAS.2012.6291947

Moradi, F., Wisland, D., Madsen, J. K. & Mahmoodi, H. (2012). Flip-Flop Design Using Novel Pulse Generation Technique. Afhandling præsenteret på IEEE International Conference on Electronics, Circuits, and Systems, Sevilla, Spanien. http://www.ieee-icecs2012.org/index.php

Cao, T.-V., Wisland, D. T., Lande, T. S. & Moradi, F. (2012). Low phase-noise VCO utilizing modified symmetric load and partial positive feedback for FDSM. Analog Integrated Circuits and Signal Processing, 73(1), 151-160. https://doi.org/10.1007/s10470-011-9803-6

Moradi, F. (2012). Novel FinFET Device Using Asymmetric Doping. I 8th European Workshop on Silicon on Insulator Technology, Devices and Circuits: EuroSOI 2012 (s. 91-92)

Moradi, F., Gupta, S. K., Panagopoulos, G., Wisland, D., Mahmoodi, H. & Roy, K. (2011). Asymmetrically Doped FinFETs for Low-Power Robust SRAMs. I E E E Transactions on Electron Devices, 58(12), 4241 - 4249. https://doi.org/10.1109/TED.2011.2169678

Moradi, F., Wisland, D., Panagopoulos, G., Roy, K., Karakonstantis, G., Mahmoodi, H. & Madsen, J. K. (2011). Multi-level wordline driver for low power SRAMs in nano-scale CMOS technology. I Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors (s. 326-331) https://doi.org/10.1109/ICCD.2011.6081419

Moradi, F., Cao, T. V., Wisland, D. T., Aunet, S. & Mahmoodi, H. (2011). Optimal body biasing for maximizing circuit performance in 65nm CMOS technology. I Midwest Symposium on Circuits and Systems (s. 4) https://doi.org/10.1109/MWSCAS.2011.6026651

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Revideret 15.02.2026

Farshad Moradi